library IEEE;
use IEEE.std_logic_1164.all;

entity codeConverter3 is
   port( SW    : IN  std_logic_vector( 1 downto 0 );
         hex   : OUT std_logic_vector( 6 downto 0 ) );
end codeConverter3;

architecture behavioural of codeConverter3 is
begin
   process( SW )
   begin
      case SW is
         when "00" => hex <= "0000000";
         when "01" => hex <= "0011000";
         when "10" => hex <= "0001000";
         when others => hex <= "0000011";
      end case;
   end process;
end behavioural;


